ATMEGA169P-16MCU【PDF 94/274 页】MCU AVR 16K ISP FLSH 16MHZ 64QFN

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2005 Microchip Technology Inc.

Preliminary

DS41265A-page 181

PIC16F946

14.13 Master Mode

Master mode of operation is supported in firmware

using interrupt generation on the detection of the Start

and Stop conditions. The Stop (P) and Start (S) bits are

cleared from a Reset or when the SSP module is dis-

abled. The Stop (P) and Start (S) bits will toggle based

on the Start and Stop conditions. Control of the I2C bus

may be taken when the P bit is set or the bus is idle and

both the S and P bits are clear.

In Master mode, the SCL and SDA lines are manipu-

lated by clearing the corresponding TRISC<6:7> bit(s).

The output level is always low, irrespective of the

value(s) in PORTC<6:7>. So when transmitting data, a

‘1’ data bit must have the TRISC<7> bit set (input) and

a ‘0’ data bit must have the TRISC<7> bit cleared (out-

put). The same scenario is true for the SCL line with the

TRISC<6> bit. Pull-up resistors must be provided

externally to the SCL and SDA pins for proper opera-

tion of the I2C module.

The following events will cause the SSP Interrupt Flag

bit, SSPIF, to be set (SSP Interrupt will occur if

enabled):

Start condition

Stop condition

Data transfer byte transmitted/received

Master mode of operation can be done with either the

Slave mode idle (SSPM<3:0> = 1011), or with the

Slave active. When both Master and Slave modes are

enabled, the software needs to differentiate the

source(s) of the interrupt.

14.14 Multi-Master Mode

In Multi-Master mode, the interrupt generation on the

detection of the Start and Stop conditions, allows the

determination of when the bus is free. The Stop (P)

and Start (S) bits are cleared from a Reset or when the

SSP module is disabled. The Stop (P) and Start (S)

bits will toggle based on the Start and Stop conditions.

Control of the I2C bus may be taken when bit P

(SSPSTAT<4>) is set, or the bus is idle and both the S

and P bits clear. When the bus is busy, enabling the

SSP Interrupt will generate the interrupt when the Stop

condition occurs.

In Multi-Master operation, the SDA line must be moni-

tored to see if the signal level is the expected output

level. This check only needs to be done when a high

level is output. If a high level is expected and a low

level is present, the device needs to release the SDA

and SCL lines (set TRISC<6:7>). There are two

stages where this arbitration can be lost, these are:

Address Transfer

Data Transfer

When the slave logic is enabled, the slave continues

to receive. If arbitration was lost during the address

transfer stage, communication to the device may be in

progress. If addressed, an ACK pulse will be gener-

ated. If arbitration was lost during the data transfer

stage, the device will need to re-transfer the data at a

later time.

14.14.1

CLOCK SYNCHRONIZATION AND

THE CKP BIT

When the CKP bit is cleared, the SCL output is forced

to ‘0’; however, setting the CKP bit will not assert the

SCL output low until the SCL output is already sampled

low. Therefore, the CKP bit will not assert the SCL line

until an external I2C master device has already

asserted the SCL line. The SCL output will remain low

until the CKP bit is set and all other devices on the I2C

bus have deasserted SCL. This ensures that a write to

the CKP bit will not violate the minimum high time

requirement for SCL (see Figure 14-12).

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